The present invention relates to a DC-DC converter and a method for controlling a DC-DC converter.
In the prior art, electronic devices, such as a notebook computer or a game gadget, incorporates a plurality of semiconductor devices. To keep the operational voltage supplied to the semiconductor devices constant, a DC-DC converter is used to maintain constant battery voltage, which tends to fluctuate, by converting battery voltage to constant voltage (operational voltage) (e.g., Japanese Laid-Open Patent Publication Nos. 2000-69746, 2000-184612, and 2001-352750).
The conversion efficiency of DC-DC converters must be improved for electronic devices to be used more widely. This is because the conversion efficiency of a DC-DC converter determines the battery operation time of an electronic device. For example, in an electronic device of which power consumption is 1 Wh, when operating the electronic device with a 10 Wh battery, if the ideal conversion efficiency of the DC-DC converter is 100%, the operation time of the battery is ten hours. However, if the conversion efficiency is 50%, the battery operation time decreases to five hours.
In a switching regulator type DC-DC converter, the conversion efficiency is improved by employing synchronous rectification or by employing a switching transistor, such as an n-type field effect transistor (FET) as a main switching transistor (e.g., Japanese Laid-Open Patent Publication No. 2000-197349, pages 7–8, FIG. 8).
In synchronous rectification, an FET is used in lieu of a flywheel diode as a circuit for rectifying output in a DC-DC converter. Synchronous rectification decreases voltage drops and achieves high conversion efficiency. Synchronous rectification is necessary to achieve high conversion efficiency especially for a DC-DC converter having low output voltage.
Among switching regulator type DC-DC converters, a voltage drop type that converts high voltage to low voltage has a high conversion efficiency of 95% to 96%. A prior art example of a synchronous rectification voltage drop type DC-DC converter is shown in FIG. 1. The DC-DC converter 1 is incorporated in an electronic device (e.g., notebook personal computer) and converts input voltage from a battery (not shown) to an output voltage Vout, which is used to operate CPUs and their peripheral circuits.
The DC-DC converter 1 includes a control circuit 2 and a plurality of externally connected devices that are configured on a single chip of a semiconductor device. The control circuit 2 generates a first drive signal SG1, which is provided to the gate of a main switching transistor T1 (specifically, a p-type FET). The source of the transistor T1 is supplied with the input voltage Vin. The drain of the main switching transistor (hereafter referred to as main transistor) T1 is connected to the drain of a synchronous rectification transistor T2 (specifically, an n-type FET). The gate of the synchronous rectification transistor (hereafter referred to as rectifying transistor) T2 is provided with a second drive signal SG2 of the control circuit 2. The source of the transistor T2 is grounded.
The drain of the main transistor T1 is connected to an output terminal 3 via a choke coil L1. The output terminal is grounded via a smoothing capacitor C1. The drain of the main transistor T1 is further connected to the cathode of a flywheel diode D1, and the anode of the diode D1 is grounded.
The control circuit 2 includes voltage dividing resistors R1 and R2, an error amplifier 4, a triangular wave oscillator 5, a PWM comparator 6, and drive circuits 7a and 7b. Further, the control circuit 2 generates the first and second drive signals SG1 and SG2. The first and second drive signals SG1 and SG2 respectively control the operation of the transistors T1 and T2.
In the control circuit 2, the voltage dividing resistors R1 and R2 divide the output voltage Vout. The divisional voltage is supplied to the inverting input terminal of the error amplifier 4. The non-inverting input terminal of the error amplifier 4 is supplied with a reference voltage e1 (first reference voltage). The error amplifier 4 compares the divisional voltage, which corresponds to the output voltage Vout, to amplify the voltage difference between the divisional voltage and the reference voltage and generates an error output signal A1.
The error output signal A1 is provided to the non-inverting terminal of the PWM comparator 6. The inverting input terminal of the PWM comparator 6 is provided with a triangular wave signal, which has a predetermined cycle, from the triangular wave oscillator 5. The PWM comparator 6 compares the error output signal A1 with the triangular wave signal to generate a PWM output signal P1 having a predetermined duty ratio in accordance with the comparison result. The PWM output signal P1 controls the activation and inactivation of the main transistor T1 to maintain the output voltage Vout at a constant state.
FIG. 2 is a waveform diagram showing the operation of the control circuit 2. In the control circuit 2, the voltage fluctuation of the error output signal A1 is large when the difference between the divisional voltage and the reference voltage e1 is large and small when the voltage difference between the divisional voltage and the reference voltage e1 is small.
The PWM comparator 6 generates the PWM output signal P1 at a high level when the triangular wave signal is lower than the error output signal A1 and generates the PWM output signal P1 at a low level when the triangular wave signal is higher than the output signal A1. Accordingly, when the voltage of the error output signal A1 increases, the pulse width of the PWM output signal P1 increases (i.e., the pulse width during which the signal P1 is high).
The PWM output signal P1 is inverted by a drive circuit 7a (specifically, an inverter circuit) and provided to the gate of the main transistor T1 as the first drive signal SG1. Thus, when the pulse width of the PWM output signal P1 increases, the ON time of the transistor T1 increases. On the other hand, when the pulse width of the PWM output signal P1 decreases, the ON time of the transistor T1 decreases.
In the DC-DC converter 1, the PWM output signal P1 controls the activation and inactivation of the main transistor T1 so that the output voltage Vout becomes equal to the constant voltage set by the reference voltages e1 and the voltage dividing resistors R1 and R2.
The PWM comparator 6 generates an inverted PWM output signal P2 having a logic level that is inverted from the PWM output signal P1. That is, the output signals P1 and P2 are output as complementary signals from the PWM comparator 6. The inverted PWM output signal P2 is provided to the gate of the rectifying transistor T2 as the second drive signal SG2 via the drive circuit 7b. 
Accordingly, the rectifying transistor T2 is inactivated when the main transistor T1 is activated, and the rectifying transistor T2 is activated when the main transistor T1 is inactivated. That is, the main transistor T1 and the rectifying transistor T2 are alternately activated by the first and second drive signals SG1 and SG2 provided from the control circuit 2.
The switching operation of the main transistor T1 smoothes output current of the main transistor T1 by means of the choke coil L1 and the smoothing capacitor C1. When the main transistor T1 is activated, the input voltage Vin is supplied to an LC circuit (i.e., smoothing circuit configured by the choke coil L1 and the smoothing capacitor C1) via the transistor T1. When the main transistor T1 is inactivated, a current path is configured with the flywheel diode T1. In this state, the energy stored in the choke coil L1 during activation of the main transistor T1 is released to the output terminal 3.
The output voltage of the output terminal 3 is represented by the next equation.Vout=Vin×Ton/(Ton+Toff)
In the equation, Ton represents the period during which the transistor T1 is activated (the activation time of the PWM output signal P1 in FIG. 2) and Toff represents the period during which the transistor T1 is inactivated (the inactivation time of the output signal P1 in FIG. 2).
Accordingly, even if the input voltage Vin fluctuates due to reasons, such as battery drainage or the environmental conditions of the electronic device, the controlling of the duty cycle of the PWM output signal guarantees that the output voltage Vout is maintained at a constant voltage.
In the DC-DC converter 1, when the main transistor T1 is inactivated, the second drive signal SG2 activates the rectifying transistor T2 and the voltage drop of the flywheel diode D1 in the forward direction is clamped. This decreases voltage drop and improves the smoothing efficiency.
In the DC-DC converter 1, a p-type FET is used as the main transistor T1. However, if an n-type FET is used as the main transistor T1 like in a DC-DC converter 1a as shown in FIG. 3, the ON resistance of the main transistor T1 decreases and reduces power loss.
When using an n-type FET as the main transistor T1, the first drive signal SG1 for driving the transistor T1 must have a voltage that is greater than the input voltage Vin. Thus, in the DC-DC converter 1a of FIG. 3, when the main transistor T1 is activated and inactivated, a charge pump generates the drive voltage of the transistor T1 by utilizing the fluctuation of the input voltage Vin between the source potential and ground potential of the main transistor T1.
More specifically, the PWM output signal P1 is provided via a drive circuit 8a to the gate of the main transistor T1. The inverted PWM output signal P2 is provided via a drive circuit 8b to the gate of the rectifying transistor T2 as the second drive signal SG2.
A series-connected circuit configured by a diode D2 and a capacitor C3 is connected between the drain and source of the main transistor T1. The cathode of the diode D22 is connected to the capacitor C3. A connection node between the diode D2 and the capacitor C3 is connected to a power supply terminal of the drive circuit 8a. The anode of the diode D2 is connected to a power supply terminal of the drive circuit 8b. Further, the anode of the diode D2 is connected to the ground via a capacitor C2.
In the DC-DC converter 1a, when the main transistor T1 is inactivated and the rectifying transistor T2 is activated, the source potential of the main transistor T1 is the ground potential. In this state, current flows via the diode D2 to the capacitor C3. The capacitor C3 is charged until its voltage becomes equal to the input voltage Vin. Then, the charged voltage of the capacitor C3 is used to output the drive signal SG1 from the drive circuit 8a and activate the main transistor T1.
When the main transistor T1 is activated, the source potential of the transistor T1 is increased to the input voltage Vin. In this state, the capacitor C3 is connected to the source of the transistor T1. Thus, the voltage supplied from the capacitor C3 to the drive circuit 8a increases and becomes greater than the input voltage Vin. Even if the source potential of the transistor T1 increases, the voltage of the first drive signal SG1 for the source potential does not change and is equal to the input voltage Vin.
The first drive signal SG1 drives the main transistor T1. In this state, the capacitor C3 has a voltage that is greater than the input voltage Vin. Further, the diode D2 functions as a reversed current prevention circuit for preventing charges of the capacitor C3 from reversely flowing towards the side of the input voltage Vin (battery voltage).
The input voltage Vin drives the main transistor T1 of the DC-DC converter 1a. In this case, power loss resulting from the gate capacitance of the main transistor T1 is represented by the next equation.PW=½×f×C×Vin^2
In the equation, f represents the switching frequency, and C represents the gate capacitance of the main switching transistor T1. Further, ^ indicates that Vin is to be raised to an exponential power (2 in this case).
The power loss PW resulting from the gate capacitance C of the transistor T1 is proportional to the switching frequency f and is proportional to the square of the input voltage Vin. Thus, a linear regulator is employed to decrease the input voltage Vin to an appropriate voltage value and use the decreased input voltage Vin in order to reduce power loss PW.
FIG. 4 shows a prior art example of a DC-DC converter 1b using a linear regulator 9. In the DC-DC converter 1b, the linear regulator 9 is provided with the input voltage Vin. The output terminal of the linear regulator 9 is connected to the anode of the diode D2 and to the power supply terminal of the drive circuit 8b. 
However, when the output is increased and the frequency is raised in the DC-DC converter 1b, the gate current flowing to the gate of the main transistor T1 increases. This produces heat in the linear regulator 9.
To reduce power loss, as shown by the broken line in the DC-DC converter 1b of FIG. 4, a diode D3 may be added between the linear regulator 9 and the output terminal 3. In this case, when the DC-DC converter 1b is activated, the output voltage of the linear regulator 9 is used as the drive voltage. When the output voltage Vout is output from the output terminal 3 at a constant voltage, the output voltage Vout is used as the drive voltage. This is preferable for reducing the power loss PW when the output voltage Vout of the DC-DC converter 1b is the optimal voltage value for the drive voltage of the main transistor T1.
In the DC-DC converter, the voltage dividing resistors R1 and R2 are arranged outside the control circuit 2 as externally connected devices. The resistance of each of the resistors R1 and R2 is altered to set the output voltage Vout as desired. In this case, the output voltage Vout is not necessarily the optimal value for the drive voltage of the main transistor T1. Thus, the technology of FIG. 4 in which the diode D3 is added cannot be employed.
In recent years, the power efficiency of semiconductor devices incorporated in electronic devices has increased. Further, the voltage of the DC-DC converter is decreasing year by year. Thus, the output voltage of the DC-DC converter cannot be used directly as the drive voltage of the main transistor T1.